Advances in technology have resulted in smaller and more powerful computing devices. For example, there currently exist a variety of portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs), and paging devices that are small, lightweight, and easily carried by users. More specifically, portable wireless telephones, such as cellular telephones and Internet Protocol (IP) telephones, can communicate voice and data packets over wireless networks. Further, many such wireless telephones include other types of devices that are incorporated therein. For example, wireless telephones can also include a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such wireless telephones can process executable instructions, including software applications, such as a web browser application, that can be used to access the Internet. As such, these wireless telephones can include significant computing capabilities.
Such computing capabilities may be enhanced via a processor that includes an instruction cache (icache) that is configured to store (in a cache line) recently or frequently executed program instructions. Instructions stored in the instruction cache may be accessed by the processor more quickly than instructions accessed from a main memory. The instruction cache includes a plurality of ways that each include a driver that corresponds to one or more cache lines (e.g., storage locations) of the instruction cache. To access a particular instruction stored in the instruction cache, all drivers may be enabled (e.g., activated) to drive (via a plurality of data lines) all the ways to a multiplexer, and the desired way may be selected by the multiplexer. However, driving all the ways for each instruction cache access expends power to drive each way, even though only a single way is ultimately selected.
To reduce power consumption, way prediction techniques have been used to predict (e.g., identify) a “next way” to be driven and thus a next cache line (e.g., instruction(s)) to be executed. By predicting the “next way” (i.e., a location of the next instruction to be executed), only a single way needs to be driven. However, previous way prediction techniques are susceptible to frequent misprediction (e.g., predicting an incorrect way) which results in a performance loss and a power penalty experienced by the processor to correct the misprediction and access the correct next way.
For example, a first technique stores the last (previous) “next way” for each cache line (i.e., a single “next way”). Based on the single “next way”, the instruction cache enables a single driver that corresponds to the single “next way.” When the correct way is not driven (i.e., not provided to the multiplexer), a misprediction occurs and a second access to the instruction cache data array is performed that drives the correct way (based on a completed tag lookup operation or a signal provided from control logic). When using the first technique, accuracy of predicting the correct “next way” is an issue because predictability of a given program (e.g., multiple instructions) may be erratic. Accordingly, the last “next way” for a cache line is not necessarily a good predictor and frequent mispredictions occur.
A second technique assigns a confidence value to a way prediction to decide whether the way prediction is likely to result in selecting (i.e., identifying) the correct way. If the confidence value for a single way prediction is not high enough, all of the drivers are enabled. A third technique stores a predicted “next way” in a branch target buffer (e.g., a trace cache) to be used when a branch type instruction is identified. The stored predicted “next way” may have a high accuracy rate, but branches may not be taken very often and thus the third technique is only useful in situations where a branch is taken after execution of a current instruction.